Recently, stacked die packaging with through-silicon-via technology has been intensively studied because of its higher performance, higher operation speed and smaller volume. The major challenge in through-silicon-via stacking is the realization of high aspect ratio vias, which are passivated and filled with conductive material.
In general, through-silicon-vias can be produced using via-first or via-last technologies. In via-last technologies the through-silicon-vias are produced after the transistor process. In via-first technologies the through-silicon-vias are produced before the transistor process. In via-first-technologies the through-silicon-vias are exposed to the full thermal budget of the high temperature transistor process.
The high thermal budget encountered by the through-silicon-vias in a via-first-technology influences the specific resistivity of the through-silicon-vias. Due to the high temperatures during the transistor process, applicability of metals with a low specific resistivity as a conductive filling material inside the through-silicon-vias is limited.
Polycrystalline silicon has been proposed as a conductive filling material for through-silicon-vias in a via-first-technology. The polycrystalline silicon may be deposited inside the through-silicon-vias by chemical vapor deposition. To allow for a high throughput of polycrystalline silicon filling, silicon posts may be left behind inside the vias after the formation of the through-silicon-vias. Since polycrystalline silicon grows from the side walls of the vias, smaller gaps between the silicon posts inside the vias reduce the filling time.
The high thermal budget of the following transistor process, however, leads to a specific resistivity of 2 mΩ cm to 10 mΩ cm. It is, however, regarded as desirable to obtain through-silicon-vias with a filling material with a specific resistivity below 1 mΩ cm.